[Bug target/106101] [12/13 Regression] ICE in reg_bitfield_target_p

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106101

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|rtl-optimization            |target
           Priority|P3                          |P2

--- Comment #4 from Richard Biener <rguenth at gcc dot gnu.org> ---
(In reply to Segher Boessenkool from comment #3)
> STRICT_LOW_PART is required to contain a SUBREG though.

So

Trying 23 -> 24:
   23: r77:DI=[r85:DI]
      REG_DEAD r85:DI
   24: strict_low_part(r71:SI)=r77:DI#4
      REG_DEAD r77:DI
Successfully matched this instruction:
(set (strict_low_part (reg/v:SI 71 [ yyval ]))
    (mem/f:SI (plus:DI (reg:DI 85)
            (const_int 4 [0x4])) [2 *_3+4 S4 A32]))
allowing combination of insns 23 and 24

just exposes the issue that RTL expansion produces:

;; MEM[(char * *)&yyval] = _4;

(insn 23 22 24 (set (reg/f:DI 77)
        (mem/f:DI (reg/f:DI 62 [ _3 ]) [2 *_3+0 S8 A64])) "/tmp/y.tab.i":41:23
-1
     (nil))

(insn 24 23 0 (set (strict_low_part (reg/v:SI 71 [ yyval ]))
        (subreg:SI (reg/f:DI 77) 4)) "/tmp/y.tab.i":41:23 -1
     (nil))

which is emitted via

#3  0x0000000001fe5354 in gen_movstrictsi (operand0=0x7ffff6a49d20, 
    operand1=0x7ffff6a4e438) at insn-emit.cc:11776
#4  0x00000000019163e5 in s390_expand_insv (dest=0x7ffff6a4e3f0, 
    op1=0x7ffff68c8690, op2=0x7ffff68c8690, src=0x7ffff6a4e3d8)
    at /space/rguenther/src/gcc/gcc/config/s390/s390.cc:6530
#5  0x00000000020373a8 in gen_insv (operand0=0x7ffff6a4e3f0, 
    operand1=0x7ffff68c8690, operand2=0x7ffff68c8690, operand3=0x7ffff6a4e3d8)
    at /space/rguenther/src/gcc/gcc/config/s390/s390.md:4217
...
#8  0x0000000001242f07 in maybe_expand_insn (icode=CODE_FOR_insv, nops=4, 
    ops=0x7fffffffc500) at /space/rguenther/src/gcc/gcc/optabs.cc:7998
#9  0x0000000000e43d46 in store_bit_field_using_insv (insv=0x7fffffffc7a0, 
    op0=0x7ffff6a49d20, op0_mode=SImode, bitsize=32, bitnum=32, 

;
; movstrictsi instruction pattern(s).
;

(define_insn "movstrictsi"
  [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
                         (match_operand:SI 1 "general_operand" "d,R,T,t"))]
  "TARGET_ZARCH"
  "@
   lr\t%0,%1
   l\t%0,%1
   ly\t%0,%1
   ear\t%0,%1"
  [(set_attr "op_type" "RR,RX,RXY,RRE")
   (set_attr "type" "lr,load,load,*")
   (set_attr "cpu_facility" "*,*,longdisp,*")
   (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])

all of which is ancient code ...

target issue after all.