[Bug target/105854] ICE: in extract_constrain_insn, at recog.cc:2692 (insn does not satisfy its constraints: sse2_lshrv1ti3)

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105854

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-12 branch has been updated by hongtao Liu
<liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:c45a9752f15bbc37d8efda0e29af5a2bfd53729d

commit r12-8462-gc45a9752f15bbc37d8efda0e29af5a2bfd53729d
Author: liuhongt <hongtao.liu@intel.com>
Date:   Mon Jun 6 13:39:19 2022 +0800

    Fix insn does not satisfy its constraints: sse2_lshrv1ti3

    21114(define_insn_and_split "ssse3_palignrdi"
    21115  [(set (match_operand:DI 0 "register_operand" "=y,x,Yv")
    21116        (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv")
    21117                    (match_operand:DI 2 "register_mmxmem_operand"
"ym,x,Yv")
    21118                    (match_operand:SI 3
"const_0_to_255_mul_8_operand")]
    21119                   UNSPEC_PALIGNR))]
    21120  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"

    Alternative 2 requires Yw instead of Yv since it's splitted to vpsrldq
    which requires AVX512VL & AVX512BW for evex version.

    gcc/ChangeLog:

            PR target/105854
            * config/i386/sse.md (ssse3_palignrdi): Change alternative 2
            from Yv to Yw.