[Bug target/106265] RISC-V SPEC2017 507.cactu code bloat due to address generation

[vineet.gupta at linux dot dev]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106265

--- Comment #10 from Vineet Gupta <vineet.gupta at linux dot dev> ---
Created a small test case which emulates generation of 2 split consts. 

void foo(void)
{
        bar(2072, 2096);
}

253r.expand has 4 instructions: Pair of LI 4096 + ADDI for each const.
260r.fwprop1 prunes out the redundant insn 7. However it runs before
300r.reload. The original issue is reload inserting the insns so no way to
prune these out.

---253r.expand----
(insn 5 2 6 2 (set (reg:DI 72)
        (const_int 4096 [0x1000])) "const-load.c":5:2 -1
     (nil))
(insn 6 5 7 2 (set (reg:DI 11 a1)
        (plus:DI (reg:DI 72)
            (const_int -2000 [0xfffffffffffff830]))) "const-load.c":5:2 -1
     (expr_list:REG_EQUAL (const_int 2096 [0x830])
        (nil)))
(insn 7 6 8 2 (set (reg:DI 73)
        (const_int 4096 [0x1000])) "const-load.c":5:2 -1
     (nil))
(insn 8 7 9 2 (set (reg:DI 10 a0)
        (plus:DI (reg:DI 73)
            (const_int -2024 [0xfffffffffffff818]))) "const-load.c":5:2 -1
     (expr_list:REG_EQUAL (const_int 2072 [0x818])
        (nil)))

---300r.reload----
(insn 5 2 6 2 (set (reg:DI 10 a0 [72])
        (const_int 4096 [0x1000])) "const-load.c":5:2 139 {*movdi_64bit}
     (expr_list:REG_EQUIV (const_int 4096 [0x1000])
        (nil)))
(insn 6 5 8 2 (set (reg:DI 11 a1)
        (plus:DI (reg:DI 10 a0 [72])
            (const_int -2000 [0xfffffffffffff830]))) "const-load.c":5:2 4
{adddi3}
     (expr_list:REG_EQUAL (const_int 2096 [0x830])
        (nil)))
(insn 8 6 9 2 (set (reg:DI 10 a0)
        (plus:DI (reg:DI 10 a0 [72])
            (const_int -2024 [0xfffffffffffff818]))) "const-load.c":5:2 4
{adddi3}
     (expr_list:REG_EQUAL (const_int 2072 [0x818])
        (nil)))