[Bug target/106180] [13 Regression] ICE in extract_insn, at recog.cc:2791 since r13-1418-g73f942c08deef3

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106180

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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                 CC|                            |jakub at gcc dot gnu.org

--- Comment #1 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
The ICE is because
(define_expand "vec_unpacks_lo_v4sf"
  [(set (match_operand:V2DF 0 "register_operand")
        (float_extend:V2DF
          (vec_select:V2SF
            (match_operand:V4SF 1 "vector_operand")
            (parallel [(const_int 0) (const_int 1)]))))]
  "TARGET_SSE2")
used to match the sse2_cvtps2pd both when operands[1] was REG or MEM, but now
it doesn't.
I think the r13-1418 change was just wrong.  It is fine to add a pattern with
V2SF input rather than vec_select of first half of V4SF input, but I don't
understand why you need to restrict one to memory_operand and the other to
register_operand, why vector_operand "vm" can't be used for both.
Not doing that ties hands of the register allocator, if something is memory
during expansion, it would be always in memory, if something isn't memory, it
couldn't ever be memory.
Is your concern not getting a SIGSEGV if first 2 SF elts are at the end of a
page and 2 further SF elts are in a non-mapped page?