[Bug rtl-optimization/104059] [12 Regression] cprop_hardreg propgates hard registers for mov instructions between different REG_CLASS without considering cost

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104059

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|x86_64-*-* i?86-*-*         |x86_64-*-* i?86-*-*
                   |aarch64*-*-*                |

--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Andrew Pinski from comment #3)
> Figures. I might take a look tomorrow.


Before in GCC 11 for gimple level:
  vect_sum_26.13_34 = VIEW_CONVERT_EXPR<vector(4) int>(vect__7.9_48);
  _32 = (vector(4) unsigned int) vect_sum_26.13_34;
  _31 = VEC_PERM_EXPR <_32, { 0, 0, 0, 0 }, { 2, 3, 4, 5 }>;
  _25 = _31 + _32;
  _19 = VEC_PERM_EXPR <_25, { 0, 0, 0, 0 }, { 1, 2, 3, 4 }>;
  _18 = _19 + _25;
  stmp_sum_26.14_17 = BIT_FIELD_REF <_18, 32, 0>;
  _44 = VEC_PERM_EXPR <vect__7.9_48, { 0, 0, 0, 0 }, { 2, 3, 4, 5 }>;
  _38 = _44 + vect__7.9_48;
  _37 = VEC_PERM_EXPR <_38, { 0, 0, 0, 0 }, { 1, 2, 3, 4 }>;
  _36 = _37 + _38;
  stmp__9.12_35 = BIT_FIELD_REF <_36, 32, 0>;
  _20 = stmp_sum_26.14_17 & 65535;
  _10 = (unsigned int) _20;
  _12 = stmp__9.12_35 >> 16;
  _13 = _10 + _12;
  _14 = _13 >> 1;
  _23 = (int) _14;

After on the trunk:
  _43 = VEC_PERM_EXPR <vect__7.11_47, { 0, 0, 0, 0 }, { 2, 3, 4, 5 }>;
  _42 = _43 + vect__7.11_47;
  _41 = VEC_PERM_EXPR <_42, { 0, 0, 0, 0 }, { 1, 2, 3, 4 }>;
  _34 = _41 + _42;
  stmp__9.14_33 = BIT_FIELD_REF <_34, 32, 0>;
  _37 = stmp__9.14_33 & 65535;
  _12 = stmp__9.14_33 >> 16;
  _13 = _12 + _37;
  _14 = _13 >> 1;
  _23 = (int) _14;

As you can see the number of adds and PERM is better. I don't see anything that
should be done on the gimple level, the gimple level looks decent now.
Basically what was _10  previously is now _37 and all of the extra casts were
removed.