[Bug target/104502] [12 Regression] ICE: in extract_constrain_insn, at recog.cc:2670: insn does not satisfy its constraints with -O -flive-range-shrinkage -march=barcelona -fstack-protector-all -mavx512f

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104502

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:0538d42cdd68f6b65d72ed7768f1d00ba44f8631

commit r12-7212-g0538d42cdd68f6b65d72ed7768f1d00ba44f8631
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sat Feb 12 11:17:41 2022 +0100

    i386: Fix up cvtsd2ss splitter [PR104502]

    The following testcase ICEs, because AVX512F is enabled, AVX512VL is not,
    and the cvtsd2ss insn has %xmm0-15 as output operand and %xmm16-31 as
    input operand.  For output operand %xmm16+ the splitter just gives up
    in such case, but for such input it just emits vmovddup which requires
    AVX512VL if either operand is EXT_REX_SSE_REG_P (when it is 128-bit).

    The following patch fixes it by treating that case like the pre-SSE3
    output != input case - move the input to output and do everything on
    the output reg which is known to be < %xmm16.

    2022-02-12  Jakub Jelinek  <jakub@redhat.com>

            PR target/104502
            * config/i386/i386.md (cvtsd2ss splitter): If operands[1] is xmm16+
            and AVX512VL isn't available, move operands[1] to operands[0]
first.

            * gcc.target/i386/pr104502.c: New test.