[Bug target/103627] ICE: in extract_insn, at recog.c:2769 (error: unrecognizable insn)
cvs-commit at gcc dot gnu.org
gcc-bugzilla@gcc.gnu.org
Mon Feb 7 05:48:50 GMT 2022
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103627
--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kewen Lin <linkw@gcc.gnu.org>:
https://gcc.gnu.org/g:8103623923ac4ea19b97a369979d4bd5731aab57
commit r12-7078-g8103623923ac4ea19b97a369979d4bd5731aab57
Author: Kewen Lin <linkw@linux.ibm.com>
Date: Sun Feb 6 21:29:32 2022 -0600
rs6000: Disable MMA if no VSX support [PR103627]
As PR103627 shows, there is an unexpected case where !TARGET_VSX
and TARGET_MMA co-exist. As ISA3.1 claims, SIMD is a requirement
for MMA. By looking into the ICE, I noticed that the current
MMA implementation depends on vector pairs load/store which use
VSX register, but we don't have a separated option to control
Power10 vector support and Segher pointed out "-mpower9-vector is
a workaround that should go away" and more explanations in [1].
So this patch makes MMA require VSX instead.
[1] https://gcc.gnu.org/pipermail/gcc-patches/2022-January/589303.html
gcc/ChangeLog:
PR target/103627
* config/rs6000/rs6000.cc (rs6000_option_override_internal):
Disable
MMA if !TARGET_VSX.
gcc/testsuite/ChangeLog:
PR target/103627
* gcc.target/powerpc/pr103627-1.c: New test.
* gcc.target/powerpc/pr103627-2.c: New test.
More information about the Gcc-bugs
mailing list