[Bug target/106694] Redundant move instructions in ARM SVE intrinsics use cases

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106694

--- Comment #6 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
(In reply to Andrew Pinski from comment #5)
> (In reply to JuzheZhong from comment #4)
> > No. I am not saying the issue of "movprfx". I am saying the issue of the
> > redundant "mov" instructions.:
> >         mov     z5.d, z24.d
> >         mov     z4.d, z25.d
> >         mov     z3.d, z26.d
> >         mov     z2.d, z27.d
> > 
> > 
> > This is the issue that "subreg" didn't propagate across the basic block.
> 
> Oh ld4 issue. I thought there was another bug filed against that. The
> problem is even without SVE too IIR.

Recently, I found LLVM optimize this kind of issues. This "subreg" issues are
handled by register coalescing. I wonder if there is someone can implement
this.

Besides, I am working on pushing codes of RVV support to RISC-V support. I have
done register coalescing for RVV and open source them in RISC-V foundation
repo.

I don't whether my register coalescing is appropriate to push upstream:
https://github.com/riscv-collab/riscv-gcc/blob/riscv-gcc-rvv-next/gcc/ira-coalesce.cc

If this is not appropriate to the global codes. I will try to make it inside
RISC-V port withou changing ira.cc.