[Bug target/102252] svbool_t with SVE can generate invalid assembly

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102252

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:512b383534785f9fc021e700a1fdda86cf0f3fe7

commit r12-3490-g512b383534785f9fc021e700a1fdda86cf0f3fe7
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Mon Sep 13 15:40:28 2021 +0100

    aarch64: PR target/102252 Invalid addressing mode for SVE load predicate

    In the testcase we generate invalid assembly for an SVE load predicate
instruction.
    The RTL for the insn is:
    (insn 9 8 10 (set (reg:VNx16BI 68 p0)
            (mem:VNx16BI (plus:DI (mult:DI (reg:DI 1 x1 [93])
                        (const_int 8 [0x8]))
                    (reg/f:DI 0 x0 [92])) [2 work_3(D)->array[offset_4(D)]+0 S8
A16]))

    That addressing mode is not valid for the instruction [1] as it only
accepts the addressing mode:
    [<Xn|SP>{, #<imm>, MUL VL}]

    This patch rejects the register index form for SVE predicate modes.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    [1]
https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions/LDR--predicate---Load-predicate-register-

    gcc/ChangeLog:

            PR target/102252
            * config/aarch64/aarch64.c (aarch64_classify_address): Don't allow
            register index for SVE predicate modes.

    gcc/testsuite/ChangeLog:

            PR target/102252
            * g++.target/aarch64/sve/pr102252.C: New test.