[Bug middle-end/103431] [12 Regression] wrong code with -O -fno-tree-bit-ccp -fno-tree-dominator-opts since r12-4853-g2a83259f837e5cbd

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103431

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:f7e4f57f1c7883721b6f5ad48953e10ebfb5a756

commit r12-5558-gf7e4f57f1c7883721b6f5ad48953e10ebfb5a756
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sat Nov 27 13:02:06 2021 +0100

    x86: Fix up x86_{,64_}sh{l,r}d patterns [PR103431]

    The following testcase is miscompiled because the x86_{,64_}sh{l,r}d
    patterns don't properly describe what the instructions do.  One thing
    is left out, in particular that there is initial count &= 63 for
    sh{l,r}dq and initial count &= 31 for sh{l,r}d{l,w}.  And another thing
    not described properly, in particular the behavior when count (after the
    masking) is 0.  The pattern says it is e.g.
    res = (op0 << op2) | (op1 >> (64 - op2))
    but that triggers UB on op1 >> 64.  For op2 0 we actually want
    res = (op0 << op2) | 0
    When constants are propagated to these patterns during RTL optimizations,
    both such problems trigger wrong-code issues.
    This patch represents the patterns as e.g.
    res = (op0 << (op2 & 63)) | (unsigned long long) ((uint128_t) op1 >> (64 -
(op2 & 63)))
    so there is both the initial masking and op2 == 0 behavior results in
    zero being ored.
    The patch introduces alternate patterns for constant op2 where
    simplify-rtx.c will fold those expressions into simple numbers,
    and define_insn_and_split pre-reload splitter for how the patterns
    looked before into the new form, so that it can pattern match during
    combine even computations that assumed the shift amount will be in
    the range of 1 .. bitsize-1.

    2021-11-27  Jakub Jelinek  <jakub@redhat.com>

            PR middle-end/103431
            * config/i386/i386.md (x86_64_shld, x86_shld, x86_64_shrd,
x86_shrd):
            Change insn pattern to accurately describe the instructions.
            (*x86_64_shld_1, *x86_shld_1, *x86_64_shrd_1, *x86_shrd_1): New
            define_insn patterns.
            (*x86_64_shld_2, *x86_shld_2, *x86_64_shrd_2, *x86_shrd_2): New
            define_insn_and_split patterns.
            (*ashl<dwi>3_doubleword_mask, *ashl<dwi>3_doubleword_mask_1,
            *<insn><dwi>3_doubleword_mask, *<insn><dwi>3_doubleword_mask_1,
            ix86_rotl<dwi>3_doubleword, ix86_rotr<dwi>3_doubleword): Adjust
            splitters for x86_{,64_}sh{l,r}d pattern changes.

            * gcc.dg/pr103431.c: New test.