[Bug target/103271] ICE in assign_stack_temp_for_type with -ftrivial-auto-var-init=pattern and VLAs and -mno-strict-align on riscv64

[rguenther at suse dot de]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103271

--- Comment #3 from rguenther at suse dot de <rguenther at suse dot de> ---
On Mon, 22 Nov 2021, qinzhao at gcc dot gnu.org wrote:

> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103271
> 
> qinzhao at gcc dot gnu.org changed:
> 
>            What    |Removed                     |Added
> ----------------------------------------------------------------------------
>                  CC|                            |qinzhao at gcc dot gnu.org
> 
> --- Comment #1 from qinzhao at gcc dot gnu.org ---
> was not able to repeat this failure yet due to:
> 
> 1. cannot find a riscv machine either in my company or in gcc farm.
> 2. tried to build a cross-compiler on riscv64 from a x86 platform, but always
> failed.
> 
> is there a good documentation to build cross-compiler?

You should be able to simply do

 ../configure --target=riscv64-linux
 make all-gcc

and use the built gcc/cc1 to debug such ICEs.