[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code since r11-7807-gbe70bb5e
cvs-commit at gcc dot gnu.org
gcc-bugzilla@gcc.gnu.org
Fri Mar 26 17:12:44 GMT 2021
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766
--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Vladimir Makarov <vmakarov@gcc.gnu.org>:
https://gcc.gnu.org/g:0d37e2d3ead072ba57e03fcb97a041504a22e721
commit r11-7864-g0d37e2d3ead072ba57e03fcb97a041504a22e721
Author: Vladimir Makarov <vmakarov@redhat.com>
Date: Fri Mar 26 17:09:24 2021 +0000
[PR99766] Consider relaxed memory associated more with memory instead of
special memory.
Relaxed memory should be considered more like memory then special memory.
gcc/ChangeLog:
PR target/99766
* ira-costs.c (record_reg_classes): Put case with
CT_RELAXED_MEMORY adjacent to one with CT_MEMORY.
* ira.c (ira_setup_alts): Ditto.
* lra-constraints.c (process_alt_operands): Ditto.
* recog.c (asm_operand_ok): Ditto.
* reload.c (find_reloads): Ditto.
gcc/testsuite/ChangeLog:
PR target/99766
* g++.target/aarch64/sve/pr99766.C: New.
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