[Bug target/101325] [12 Regression] arm: Wrong code with MVE vcmpeqq intrinsic since r12-671-gd083fbf72

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101325

Christophe Lyon <clyon at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |ASSIGNED
   Last reconfirmed|                            |2021-07-07
     Ever confirmed|0                           |1

--- Comment #4 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Before r12-671, in combine we have:
(insn 7 4 8 2 (set (reg:HI 117)
        (unspec:HI [
                (reg:V16QI 119)
                (reg:V16QI 120)
            ] VCMPEQQ_S)) {mve_vcmpeqq_v16qi}
     (expr_list:REG_DEAD (reg:V16QI 120)
        (expr_list:REG_DEAD (reg:V16QI 119)
            (nil))))
(note 8 7 14 2 NOTE_INSN_DELETED)
(insn 14 8 15 2 (set (reg/i:SI 0 r0)
        (zero_extend:SI (reg:HI 117))) "pr101325.c":7:1 1019
{*thumb2_zero_extendhisi2_v6}
     (expr_list:REG_DEAD (reg:HI 117)
        (nil)))


After the patch:
(insn 7 4 8 2 (set (reg:HI 117)
        (eq:HI (reg:V16QI 119)
            (reg:V16QI 120))) {mve_vcmpeqq_v16qi}
     (expr_list:REG_DEAD (reg:V16QI 120)
        (expr_list:REG_DEAD (reg:V16QI 119)
            (nil))))
(note 8 7 14 2 NOTE_INSN_DELETED)
(insn 14 8 15 2 (set (reg/i:SI 0 r0)
        (and:SI (subreg:SI (reg:HI 117) 0)
            (const_int 1 [0x1]))) "pr101325.c":7:1 90 {*arm_andsi3_insn}
     (expr_list:REG_DEAD (reg:HI 117)
        (nil)))