[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #74 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Christophe Lyon <clyon@gcc.gnu.org>:

https://gcc.gnu.org/g:1a6306420090409cb397e2e042256eb1905f415f

commit r11-6711-g1a6306420090409cb397e2e042256eb1905f415f
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Thu Oct 15 17:13:59 2020 +0000

    arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics

    This patch adds implementations for vceqq_p64, vceqz_p64 and
    vceqzq_p64 intrinsics.

    vceqq_p64 uses the existing vceq_p64 after splitting the input vectors
    into their high and low halves.

    vceqz[q] simply call the vceq and vceqq with a second argument equal
    to zero.

    The added (executable) testcases make sure that the poly64x2_t
    variants have results with one element of all zeroes (false) and the
    other element with all bits set to one (true).

    2021-01-15  Christophe Lyon  <christophe.lyon@linaro.org>

            gcc/
            PR target/71233
            * config/arm/arm_neon.h (vceqz_p64, vceqq_p64, vceqzq_p64): New.

            gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/advsimd-intrinsics/p64_p128.c: Add tests for
            vceqz_p64, vceqq_p64 and vceqzq_p64.