[Bug target/97417] RISC-V Unnecessary andi instruction when loading volatile bool

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417

--- Comment #61 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jim Wilson <wilson@gcc.gnu.org>:

https://gcc.gnu.org/g:18fabc35f47f0abf4ec14d147098ec4e0734d2a3

commit r11-7237-g18fabc35f47f0abf4ec14d147098ec4e0734d2a3
Author: Levy Hsu <admin@levyhsu.com>
Date:   Sat Feb 13 12:26:33 2021 -0800

    RISC-V: Avoid zero/sign extend for volatile loads.  Fix for 97417.

    This expands sub-word loads as a zero/sign extended load, followed by
    a subreg.  This helps eliminate unnecessary zero/sign extend insns after
    the load, particularly for volatiles, but also in some other cases.
    Testing shows that it gives consistent code size decreases.

    Tested with riscv32-elf rv32imac/ilp32 and riscv64-linux rv64gc/lp064d
    builds and checks.  Some -gsplit-stack tests fail with the patch, but
    this turns out to be an existing bug with the split-stack support that
    I hadn't noticed before.  It isn't a bug in this patch.  Ignoring that
    there are no regressions.

    Committed.

            gcc/
            PR target/97417
            * config/riscv/riscv-shorten-memrefs.c (pass_shorten_memrefs): Add
            extend parameter to get_si_mem_base_reg declaration.
            (get_si_mem_base_reg): Add extend parameter.  Set it.
            (analyze): Pass extend arg to get_si_mem_base_reg.
            (transform): Likewise.  Use it when rewriting mems.
            * config/riscv/riscv.c (riscv_legitimize_move): Check for subword
            loads and emit sign/zero extending load followed by subreg move.