[Bug rtl-optimization/98287] [10/11 Regression] ICE: in expand_expr_real_2, at expr.c:10000 with -O2 -fno-tree-ccp -fno-tree-forwprop

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98287

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:1b5572edb8caaed2f31a7235b8c58628da6bdb8f

commit r11-7050-g1b5572edb8caaed2f31a7235b8c58628da6bdb8f
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Feb 3 09:04:26 2021 +0100

    i386: Remove V1DImode shift expanders [PR98287]

    On Tue, Feb 02, 2021 at 02:23:55PM +0100, Richard Biener wrote:
    > All I say is that the x86 target
    > should either not advertise V1DF shifts or advertise the basic
    > ops that reasonable simplification would expect to exist.

    The backend has several V1?Imode shifts, but optab only for those V1DImode
    ones:

    grep '[la]sh[lr]v1[qhsdtox]' tmp-mddump.md
    (define_insn ("mmx_ashlv1di3")
    (define_insn ("mmx_lshrv1di3")
    (define_insn ("avx512bw_ashlv1ti3")
    (define_insn ("avx512bw_lshrv1ti3")
    (define_insn ("sse2_ashlv1ti3")
    (define_insn ("sse2_lshrv1ti3")
    (define_expand ("ashlv1di3")
    (define_expand ("lshrv1di3")
      emit_insn (gen_sse2_lshrv1ti3 (tmp, gen_lowpart (V1TImode, operands[1]),

    I think it has been introduced with
    https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89021#c13

    Before we didn't have any V1DImode expanders (except mov/movmisalign, but
    those are needed and are supplied for other V1??mode modes too).

    This patch just removes the two V1DImode shift expanders with standard
names.

    2021-02-03  Jakub Jelinek  <jakub@redhat.com>

            PR tree-optimization/98287
            * config/i386/mmx.md (<insn><mode>3): For shifts don't enable
expander
            for V1DImode.

            * gcc.dg/pr98287.c: New test.