[Bug target/102066] aarch64: Suboptimal addressing modes for SVE LD1W, ST1W

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102066

--- Comment #2 from ktkachov at gcc dot gnu.org ---
(In reply to rsandifo@gcc.gnu.org from comment #1)
> > I guess the predicates and constraints in @aarch64_pred_mov<mode> in aarch64-sve.md should allow for the scaled address modes
> They already allow them.  I'm guessing this is an ivopts problem,
> in that it doesn't realise it can promote the unsigned iterator
> to uint64_t for a svcntw() step.

ah indeed
#include <arm_sve.h>

void foo(int n, float *x, float *y) {
    for (uint64_t i=0; i<n; i+=svcntw()) {
        svfloat32_t val = svld1_f32(svptrue_b8(), &x[i]);
        svst1_f32(svptrue_b8(), &y[i], val);
    }
}

generates good code