[Bug target/98934] Very poor code generation for SSE 8-bit vector right shift

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98934

--- Comment #4 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Andrew Pinski from comment #2)
> This is really poor with -mavx512f even. We should be able to do it like
(define_expand "vashr<mode>3"
  [(set (match_operand:VI12_128 0 "register_operand")
        (ashiftrt:VI12_128
          (match_operand:VI12_128 1 "register_operand")
          (match_operand:VI12_128 2 "nonimmediate_operand")))]
  "TARGET_XOP || (TARGET_AVX512BW && TARGET_AVX512VL)"

We can relax condition it to TARGET_AVX512F and use do things like
ix86_expand_vecop_qihi, but with qisi.