[Bug target/101882] New: modulus with input and output set to a hard register

[willschm at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101882

            Bug ID: 101882
           Summary: modulus with input and output set to a hard register
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: willschm at gcc dot gnu.org
  Target Milestone: ---

Noted on powerpc using recent GCC.
  gcc version 12.0.0 20210812 (experimental) (GCC) 


foofoo9.c:
  register a __asm__("r20");
  b() { a = a % 9 ; }

# does not occur with -O0, or with -mcpu=power8.
$ gcc  -O -mcpu=power9 foofoo9.c 

foofoo9.c: In function ‘b’:
foofoo9.c:2:19: error: unable to generate reloads for impossible constraints:
    2 | b() { a = a % 9 ; }
      |                   ^
(insn 7 9 12 2 (set (reg/v:SI 20 20 [ a ])
        (mod:SI (reg/v:SI 20 20 [ a ])
            (reg:SI 120))) "foofoo9.c":2:13 183 {*modsi3}
     (expr_list:REG_DEAD (reg:SI 120)
        (nil)))
during RTL pass: reload
foofoo9.c:2:19: internal compiler error: in process_alt_operands, at
lra-constraints.c:3108
0x101d9597 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /home/willschm/gcc/gcc-baseline/gcc/rtl-error.c:108
0x10912b4f process_alt_operands
        /home/willschm/gcc/gcc-baseline/gcc/lra-constraints.c:3108
0x10912b4f curr_insn_transform
        /home/willschm/gcc/gcc-baseline/gcc/lra-constraints.c:4102
0x10916dbb lra_constraints(bool)
        /home/willschm/gcc/gcc-baseline/gcc/lra-constraints.c:5168
0x108fc46f lra(_IO_FILE*)
        /home/willschm/gcc/gcc-baseline/gcc/lra.c:2336
0x1089be8b do_reload
        /home/willschm/gcc/gcc-baseline/gcc/ira.c:5932
0x1089be8b execute
        /home/willschm/gcc/gcc-baseline/gcc/ira.c:6118
Please submit a full bug report,