[Bug target/99748] MVE: Wrong code at -O0 with float to integer conversion
cvs-commit at gcc dot gnu.org
gcc-bugzilla@gcc.gnu.org
Tue Apr 6 08:07:16 GMT 2021
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99748
--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Alex Coplan <acoplan@gcc.gnu.org>:
https://gcc.gnu.org/g:16ea7f57891d3fe885ee55b2917208695e184714
commit r11-7999-g16ea7f57891d3fe885ee55b2917208695e184714
Author: Alex Coplan <alex.coplan@arm.com>
Date: Tue Apr 6 09:06:27 2021 +0100
arm: Fix PCS for SFmode -> SImode libcalls [PR99748]
This patch fixes PR99748 which shows us trying to pass the argument to
__aeabi_f2iz in the VFP register s0 when the library function is
expecting to use the GPR r0. It also fixes the __aeabi_f2uiz case which
was broken in the same way.
For the testcase in the PR, here is the code we generate before the
patch (with -mfloat-abi=hard -march=armv8.1-m.main+mve -O0):
main:
push {r7, lr}
sub sp, sp, #8
add r7, sp, #0
mov r3, #1065353216
str r3, [r7, #4] @ float
vldr.32 s0, [r7, #4]
bl __aeabi_f2iz
mov r3, r0
cmp r3, #1
[...]
This becomes:
main:
push {r7, lr}
sub sp, sp, #8
add r7, sp, #0
mov r3, #1065353216
str r3, [r7, #4] @ float
ldr r0, [r7, #4] @ float
bl __aeabi_f2iz
mov r3, r0
cmp r3, #1
[...]
after the patch. We see a similar change for the same testcase with a
cast to unsigned instead of int.
gcc/ChangeLog:
PR target/99748
* config/arm/arm.c (arm_libcall_uses_aapcs_base): Also use base
PCS for [su]fix_optab.
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