[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

cvs-commit at gcc dot gnu.org gcc-bugzilla@gcc.gnu.org
Mon Sep 28 16:14:06 GMT 2020


--- Comment #66 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov


commit r8-10545-gfd250940d0e3dd17302eb5e2653255c9189bfd70
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 12:03:49 2020 +0100

    AArch64: Implement missing vcls intrinsics on unsigned types

    This patch implements some missing intrinsics that perform a CLS on
unsigned SIMD types.

    Bootstrapped and tested on aarch64-none-linux-gnu.

            PR target/71233
            * config/aarch64/arm_neon.h (vcls_u8, vcls_u16, vcls_u32,
            vclsq_u8, vclsq_u16, vclsq_u32): Define.

            PR target/71233
            * gcc.target/aarch64/simd/vcls_unsigned_1.c: New test.

    (cherry picked from commit 30957092db46d8798e632feefb5df634488dbb33)

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