[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #60 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:23b4d65ef54b9ad8eb5cca65b7412d46f35d913f

commit r9-8951-g23b4d65ef54b9ad8eb5cca65b7412d46f35d913f
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 11:07:50 2020 +0100

    AArch64: Implement missing _p64 intrinsics for vector permutes

    This patch implements some missing vector permute intrinsics operating on
poly64x2_t types.
    They are implemented identically to their uint64x2_t brethren.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vtrn1q_p64, vtrn2q_p64, vuzp1q_p64,
            vuzp2q_p64, vzip1q_p64, vzip2q_p64): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/trn_zip_p64_1.c: New test.

    (cherry picked from commit e8e818399d70c5a5a3d30a54d305c6e2b92e2c66)