[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #41 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:a8ec9cc2241f4e0c387e78f23bae0100c74de6a8

commit r8-10532-ga8ec9cc2241f4e0c387e78f23bae0100c74de6a8
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 3 08:40:30 2019 +0000

    Add support for __jcvt intrinsic

    This patch implements the __jcvt ACLE intrinsic [1] that maps down to the
FJCVTZS [2] instruction from Armv8.3-a.
    No fancy mode iterators or nothing. Just a single builtin, UNSPEC and
define_insn and the associate plumbing.
    This patch also defines __ARM_FEATURE_JCVT to indicate when the intrinsic
is available.

    [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics
    [2]
https://developer.arm.com/docs/ddi0596/latest/simd-and-floating-point-instructions-alphabetic-order/fjcvtzs-floating-point-javascript-convert-to-signed-fixed-point-rounding-toward-zero

    gcc/
            PR target/71233
            * config/aarch64/aarch64.md (UNSPEC_FJCVTZS): Define.
            (aarch64_fjcvtzs): New define_insn.
            * config/aarch64/aarch64.h (TARGET_JSCVT): Define.
            * config/aarch64/aarch64-builtins.c (aarch64_builtins):
            Add AARCH64_JSCVT.
            (aarch64_init_builtins): Initialize __builtin_aarch64_jcvtzs.
            (aarch64_expand_builtin): Handle AARCH64_JSCVT.
            * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
            __ARM_FEATURE_JCVT where appropriate.
            * config/aarch64/arm_acle.h (__jcvt): Define.
            * doc/sourcebuild.texi (aarch64_fjcvtzs_hw) Document new
            target supports option.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/acle/jcvt_1.c: New test.
            * gcc.target/aarch64/acle/jcvt_2.c: New testcase.
            * lib/target-supports.exp
            (check_effective_target_aarch64_fjcvtzs_hw): Add new check for
            FJCVTZS hw.

    Co-Authored-By: Andrea Corallo  <andrea.corallo@arm.com>

    (cherry picked from commit e1d5d19ec4f84b67ac693fef5b2add7dc9cf056d)
    (cherry picked from commit 2c62952f8160bdc8d4111edb34a4bc75096c1e05)
    (cherry picked from commit d2b86e14c14020f3e119ab8f462e2a91bd7d46e5)
    (cherry picked from commit 58ae77d3ba70a2b9ccc90a90f3f82cf46239d5f1)