[Bug rtl-optimization/97170] New: Wrong optimization in fwprop pass

[rjiejie at me dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97170

            Bug ID: 97170
           Summary: Wrong optimization in fwprop pass
           Product: gcc
           Version: 8.1.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: rjiejie at me dot com
  Target Milestone: ---

insn seqs:

s1:

        __builtin_set_float_convert_mode(0);
        r1 = __builtin_load(a1, a2);
        r2 = __builtin_float_convert(r1);
        __builtin_store(a3, r2);
        __builtin_set_float_convert_mode(0);

s2:
        __builtin_set_float_convert_mode(1);
        r1 = __builtin_load(a1, a2);
        r2 = __builtin_float_convert(r1);
        __builtin_store(a3, r2);
        __builtin_set_float_convert_mode(0);


the diference of s1 and s2 only is "__builtin_set_float_convert_mode"

from beginning, the s1 mode is set 0, but s2 mode is set 1.

from optimization 'fwprop', the s2 insns seqs is deleted 

as dead code, is it gcc bug ?



builtin patten of __builtin_set_float_convert_mode:


(define_insn "target_fcvtmode"
  [(set (reg:SI FCVTMODE_REGNUM)
        (unspec_volatile:SI [(match_operand:SI 0 "csr_operand" "rK")]
UNSPECV_FCVTMODE))]
  ""
  "fcvtmode\t%1"
)


builtin patten of __builtin_set_float_convert_mode:

(define_insn "target_fcvt"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
        UNSPEC_FCVT))
   (use (reg:SI FCVTMODE_REGNUM))]
  ""
  "fcvt\t%0,%1"
)


As far as i know, __builtin_set_float_convert_mode depend on 'FCVTMODE_REGNUM'
which is from
__builtin_set_float_convert_mode, it's not dead code.

or something wrong in my pattens ?

Anyone could give me some hints ?

Thanks