[Bug other/97417] RISC-V Unnecessary andi instruction when loading volatile bool

[admin at levyhsu dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417

--- Comment #8 from Levy <admin at levyhsu dot com> ---
Created attachment 49470
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49470&action=edit
optimization fix for BUG 97417

proposing a temp patch here in case someone needs it, then I'll submit a full
patch with test case later.

Following code was added to the riscv_legitimize_move () in the
riscv-gcc/gcc/config/riscv/riscv.c

  if(mode == QImode && MEM_P (src) && REG_P (dest) && can_create_pseudo_p())
  {
    rtx temp_reg;

    if (TARGET_64BIT)
    {
      temp_reg = gen_reg_rtx (DImode);
      emit_insn(gen_zero_extendqidi2(temp_reg, src));
    }
    else
    {
      temp_reg = gen_reg_rtx (SImode);
      emit_insn(gen_zero_extendqisi2(temp_reg, src));
    }

    riscv_emit_move(dest, gen_lowpart(QImode,temp_reg));
    return true;
  }

Tested with make report-gcc, haven't done the regression/performance test yet:

========= Summary of gcc testsuite =========
                            | # of unexpected case / # of unique unexpected
case
                            |          gcc |          g++ |     gfortran |
 rv64imafdc/  lp64d/ medlow |    0 /     0 |    0 /     0 |      - |