[Bug libgomp/97291] [SIMT] Move SIMT_XCHG_* out of non-uniform execution region

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97291

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by SRINATH PARVATHANENI
<sripar01@gcc.gnu.org>:

https://gcc.gnu.org/g:377535881166969dba43794f298170978d797ef6

commit r11-4004-g377535881166969dba43794f298170978d797ef6
Author: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Date:   Fri Oct 16 11:40:25 2020 +0100

    arm: Fix wrong code generated for mve scatter store with writeback
intrinsics with -O2 (PR97271).

    This patch fixes (PR97271) the wrong code-gen for mve scatter store with
writeback intrinsics with -O2.

    $cat bug.c
    void
    foo (uint32x4_t * addr, const int offset, int32x4_t value)
    {
      vstrwq_scatter_base_wb_s32 (addr, 8, value);
    }

    $ arm-none-eabi-gcc  bug.c -S -O2 -march=armv8.1-m.main+mve
-mfloat-abi=hard -o -
    Without this patch:
    ...
    foo:
            vldrw.32        q3, [r0]
            vstrw.u32       q0, [q3, #8]!  ---> (A)
            vldr.64 d4, .L3
            vldr.64 d5, .L3+8
            vldrw.32        q3, [r0]
            vstrw.u32       q2, [q3, #8]!  ---> (B)
            bx      lr
    ...

    With this patch:
    ...
    foo:
            vldrw.32        q3, [r0]
            vstrw.u32       q0, [q3, #8]!  --> (C)
            vstrw.32        q3, [r0]
            bx      lr
    ...

    Without this patch 2 vstrw assembly instructions (A and B) are generated
for vstrwq_scatter_base_wb_s32
    intrinsic where as fix generates only one vstrw assembly instruction (C).

    gcc/ChangeLog:

    2020-10-06  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

            PR target/97291
            * config/arm/arm-builtins.c (arm_strsbwbs_qualifiers): Modify
array.
            (arm_strsbwbu_qualifiers): Likewise.
            (arm_strsbwbs_p_qualifiers): Likewise.
            (arm_strsbwbu_p_qualifiers): Likewise.
            * config/arm/arm_mve.h (__arm_vstrdq_scatter_base_wb_s64): Modify
            function definition.
            (__arm_vstrdq_scatter_base_wb_u64): Likewise.
            (__arm_vstrdq_scatter_base_wb_p_s64): Likewise.
            (__arm_vstrdq_scatter_base_wb_p_u64): Likewise.
            (__arm_vstrwq_scatter_base_wb_p_s32): Likewise.
            (__arm_vstrwq_scatter_base_wb_p_u32): Likewise.
            (__arm_vstrwq_scatter_base_wb_s32): Likewise.
            (__arm_vstrwq_scatter_base_wb_u32): Likewise.
            (__arm_vstrwq_scatter_base_wb_f32): Likewise.
            (__arm_vstrwq_scatter_base_wb_p_f32): Likewise.
            * config/arm/arm_mve_builtins.def (vstrwq_scatter_base_wb_add_u):
Remove
            expansion for the builtin.
            (vstrwq_scatter_base_wb_add_s): Likewise.
            (vstrwq_scatter_base_wb_add_f): Likewise.
            (vstrdq_scatter_base_wb_add_u): Likewise.
            (vstrdq_scatter_base_wb_add_s): Likewise.
            (vstrwq_scatter_base_wb_p_add_u): Likewise.
            (vstrwq_scatter_base_wb_p_add_s): Likewise.
            (vstrwq_scatter_base_wb_p_add_f): Likewise.
            (vstrdq_scatter_base_wb_p_add_u): Likewise.
            (vstrdq_scatter_base_wb_p_add_s): Likewise.
            * config/arm/mve.md (mve_vstrwq_scatter_base_wb_<supf>v4si): Remove
            expand.
            (mve_vstrwq_scatter_base_wb_add_<supf>v4si): Likewise.
            (mve_vstrwq_scatter_base_wb_<supf>v4si_insn): Rename pattern to ...
            (mve_vstrwq_scatter_base_wb_<supf>v4si): This.
            (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Remove expand.
            (mve_vstrwq_scatter_base_wb_p_add_<supf>v4si): Likewise.
            (mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn): Rename pattern to
...
            (mve_vstrwq_scatter_base_wb_p_<supf>v4si): This.
            (mve_vstrwq_scatter_base_wb_fv4sf): Remove expand.
            (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise.
            (mve_vstrwq_scatter_base_wb_fv4sf_insn): Rename pattern to ...
            (mve_vstrwq_scatter_base_wb_fv4sf): This.
            (mve_vstrwq_scatter_base_wb_p_fv4sf): Remove expand.
            (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise.
            (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Rename pattern to ...
            (mve_vstrwq_scatter_base_wb_p_fv4sf): This.
            (mve_vstrdq_scatter_base_wb_<supf>v2di): Remove expand.
            (mve_vstrdq_scatter_base_wb_add_<supf>v2di): Likewise.
            (mve_vstrdq_scatter_base_wb_<supf>v2di_insn): Rename pattern to ...
            (mve_vstrdq_scatter_base_wb_<supf>v2di): This.
            (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Remove expand.
            (mve_vstrdq_scatter_base_wb_p_add_<supf>v2di): Likewise.
            (mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn): Rename pattern to
...
            (mve_vstrdq_scatter_base_wb_p_<supf>v2di): This.

    gcc/testsuite/ChangeLog:

            PR target/97291
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c:
Modify.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c:
            Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c:
Likewise.
            * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c:
Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c:
Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c:
            Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c:
            Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c:
            Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c:
Likewise.
            * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c:
Likewise.