[Bug target/97271] New: [ARM MVE]: Wrong code generated for scatter store with writeback intrinsics with -O2.

[sripar01 at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97271

            Bug ID: 97271
           Summary: [ARM MVE]: Wrong code generated for scatter store with
                    writeback intrinsics with -O2.
           Product: gcc
           Version: 11.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: sripar01 at gcc dot gnu.org
  Target Milestone: ---

Created attachment 49300
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49300&action=edit
test case

$ arm-none-eabi-gcc -v
Using built-in specs.
COLLECT_GCC=/work/gnu-work/Release/build-arm-none-eabi/install/bin/arm-none-eabi-gcc
COLLECT_LTO_WRAPPER=/work/gnu-work/Release/build-arm-none-eabi/install/libexec/gcc/arm-none-eabi/11.0.0/lto-wrapper
Target: arm-none-eabi
Configured with: /work/gnu-work/Release/src/gcc/configure
--target=arm-none-eabi
--prefix=/work/gnu-work/Release/build-arm-none-eabi/install//
--with-gmp=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--with-mpfr=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--with-mpc=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--with-isl=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--disable-shared --disable-nls --disable-threads --disable-tls
--enable-checking=yes --enable-languages=c,c++,fortran --with-newlib
--with-multilib-list=rmprofile --with-pkgversion=unknown
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 11.0.0 20200930 (experimental) (unknown)

$ cat bug.c
#include "arm_mve.h"
void
foo (uint32x4_t * addr, const int offset, int32x4_t value)
{
  vstrwq_scatter_base_wb_s32 (addr, 8, value);
}

$ arm-none-eabi-gcc  bug.c -S -O2 -march=armv8.1-m.main+mve -mfloat-abi=hard -o
-
...
foo:
        @ args = 0, pretend = 0, frame = 0
        @ frame_needed = 0, uses_anonymous_args = 0
        @ link register save eliminated.
        vldrw.32        q3, [r0]
        vstrw.u32       q0, [q3, #8]!  ---> (A)
        vldr.64 d4, .L3
        vldr.64 d5, .L3+8
        vldrw.32        q3, [r0]
        vstrw.u32       q2, [q3, #8]!  ---> (B)
        bx      lr
...

Current compiler wrongly generates 2 vstrw assembly instructions, where are
only one is expected.