[Bug target/94962] Suboptimal AVX2 code for _mm256_zextsi128_si256(_mm_set1_epi8(-1))
crazylht at gmail dot com
gcc-bugzilla@gcc.gnu.org
Mon May 18 08:41:45 GMT 2020
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94962
Hongtao.liu <crazylht at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |crazylht at gmail dot com
--- Comment #1 from Hongtao.liu <crazylht at gmail dot com> ---
redudant vmovdaq xmm0, xmm0 is generated by
----
(insn:TI 7 6 14 2 (set (reg:V8SI 20 xmm0 [84])
(vec_concat:V8SI (reg:V4SI 20 xmm0 [86])
(const_vector:V4SI [
(const_int 0 [0]) repeated x4
])))
"/export/users2/liuhongt/install/gcc10_trunk/lib/gcc/x86_64-pc-linux-gnu/10.0.1/include/avxintrin.h":770:20
5296 {avx_vec_concatv8si}
(expr_list:REG_EQUIV (const_vector:V8SI [
(const_int -1 [0xffffffffffffffff]) repeated x4
(const_int 0 [0]) repeated x4
])
(nil)))
-----
could be eliminated if src operand has same regno as dest operand.
---
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 7a7ecd4be87..4ff4cf55f74 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -21123,6 +21123,9 @@
}
case 2:
case 3:
+ if (register_operand (operands[1], <ssehalfvecmode>MODE)
+ && REGNO (operands[1]) == REGNO (operand[0]))
+ return "";
switch (get_attr_mode (insn))
{
case MODE_V16SF:
---
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