[Bug target/94950] [8/9/10 regression] ICE in gcc.dg/pr94780.c on riscv64

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94950

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Jakub Jelinek
<jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:5454a13add37fa6a8eedbf9d2f6bdc63a7825e2c

commit r10-8113-g5454a13add37fa6a8eedbf9d2f6bdc63a7825e2c
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed May 6 09:40:33 2020 +0200

    riscv: Fix up riscv_atomic_assign_expand_fenv [PR94950]

    Similarly to the fixes on many other targets, riscv needs to use
TARGET_EXPR
    to avoid having the create_tmp_var_raw temporaries without proper
DECL_CONTEXT
    and not mentioned in local decls.

    2020-05-06  Jakub Jelinek  <jakub@redhat.com>

            PR target/94950
            * config/riscv/riscv-builtins.c (riscv_atomic_assign_expand_fenv):
Use
            TARGET_EXPR instead of MODIFY_EXPR for first assignment to
old_flags.