[Bug target/94133] GCC loses track of SHIFT optimization

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94133

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|rtl-optimization            |target
             Target|                            |x86_64-*-*-*

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Actually it is done by combine though the target cost model says it is not
profitable:
Trying 10 -> 15:
   10: {r84:SI=r115:SI&0x3f;clobber flags:CC;}
      REG_DEAD r115:SI
      REG_UNUSED flags:CC
   15: {r101:TI=r100:TI<<r84:SI#0;clobber flags:CC;}
      REG_DEAD r100:TI
      REG_UNUSED flags:CC
Failed to match this instruction:
(parallel [
        (set (reg:TI 101)
            (ashift:TI (reg:TI 100 [ w1 ])
                (subreg:QI (and:SI (reg:SI 115)
                        (const_int 63 [0x3f])) 0)))
        (clobber (reg:CC 17 flags))
        (set (reg:SI 84 [ _5 ])
            (and:SI (reg:SI 115)
                (const_int 63 [0x3f])))
    ])
Failed to match this instruction:
(parallel [
        (set (reg:TI 101)
            (ashift:TI (reg:TI 100 [ w1 ])
                (subreg:QI (and:SI (reg:SI 115)
                        (const_int 63 [0x3f])) 0)))
        (set (reg:SI 84 [ _5 ])
            (and:SI (reg:SI 115)
                (const_int 63 [0x3f])))
    ])
Successfully matched this instruction:
(set (reg:SI 84 [ _5 ])
    (and:SI (reg:SI 115)
        (const_int 63 [0x3f])))
Successfully matched this instruction:
(set (reg:TI 101)
    (ashift:TI (reg:TI 100 [ w1 ])
        (subreg:QI (and:SI (reg:SI 115)
                (const_int 63 [0x3f])) 0)))
rejecting combination of insns 10 and 15
original costs 4 + 32 = 36
replacement costs 4 + 36 = 40