[Bug target/94037] Runtime varies 2x just by order of two int assignments

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94037

--- Comment #5 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Richard Biener from comment #4)
> (In reply to Uroš Bizjak from comment #3)
> > (In reply to Jakub Jelinek from comment #2)
> > > The
> > >         setge   %sil
> > >         movzbl  %sil, %esi
> > > to
> > >         xorl    %esi, %esi
> > >         setge   %sil
> > 
> > This is quite important conversion, as the later avoids partial register
> > stall.
> 
> Couldn't we fix this by pretending setge and friends produce SImode
> and always emit xor + setCC?  So not rely on a peephole but emit
> the xor already during RTL expansion, eventually eliding it later
> if that's ever necessary.

xor clobbers flags, so they would be killed before setCC. OTOH, "mov $0, %reg"
doesn't clobber flags, but it also doesn't break partial reg dependency.