[Bug tree-optimization/94442] [10/11 regression] Redundant loads/stores emitted at -O3

[xiezhiheng at huawei dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94442

--- Comment #6 from xiezhiheng at huawei dot com ---
I'm trying to modify get_inner_reference to handle the case
for MEM[ptr, off].

I extract the "off" and add it to the recorded offset, then I
build a MEM[ptr, 0] and return it later.

Like this
                }
              exp = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
            }
+         else if (TREE_CODE (TREE_OPERAND (exp, 0)) == SSA_NAME)
+           {
+             tree off = TREE_OPERAND (exp, 1);
+             if (!integer_zerop (off))
+               {
+                 poly_offset_int boff = mem_ref_offset (exp);
+                 boff <<= LOG2_BITS_PER_UNIT;
+                 bit_offset += boff;
+
+                 exp = build2 (MEM_REF, TREE_TYPE (exp),
+                               TREE_OPERAND (exp, 0),
+                               build_int_cst (TREE_TYPE (off), 0));
+               }
+           }
          goto done;

        default:

Assembly with the patch looks like:
.L6:
        ldp     q3, q2, [x0, 64]
        add     w2, w2, 1
        sqadd   v1.16b, v1.16b, v3.16b
        sqadd   v0.16b, v0.16b, v2.16b
        sqadd   v1.16b, v1.16b, v3.16b
        sqadd   v0.16b, v0.16b, v2.16b
        sqadd   v3.16b, v3.16b, v1.16b
        sqadd   v2.16b, v2.16b, v0.16b
        sqadd   v1.16b, v1.16b, v3.16b
        sqadd   v0.16b, v0.16b, v2.16b
        sqadd   v1.16b, v1.16b, v3.16b
        sqadd   v0.16b, v0.16b, v2.16b
        sqadd   v3.16b, v3.16b, v1.16b
        sqadd   v2.16b, v2.16b, v0.16b
        sqadd   v1.16b, v1.16b, v3.16b
        sqadd   v0.16b, v0.16b, v2.16b
        sqadd   v5.16b, v1.16b, v3.16b
        sqadd   v4.16b, v0.16b, v2.16b
        stp     q1, q0, [x0]
        sqadd   v3.16b, v3.16b, v5.16b
        sqadd   v2.16b, v2.16b, v4.16b
        sqadd   v1.16b, v1.16b, v3.16b
        sqadd   v0.16b, v0.16b, v2.16b
        stp     q3, q2, [x0, 64]
        stp     q1, q0, [x0, 32]
        cmp     w1, w2
        bne     .L6