[Bug target/95737] PPC: Unnecessary extsw after negative less than

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95737

Segher Boessenkool <segher at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |segher at gcc dot gnu.org
                 CC|                            |segher at gcc dot gnu.org
             Target|powerpc-*-*-*               |powerpc64*-*-*
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |ASSIGNED
   Last reconfirmed|                            |2020-06-21

--- Comment #5 from Segher Boessenkool <segher at gcc dot gnu.org> ---
In gimple this already is

negativeLessThan (long long unsigned int a, long long unsigned int b)
{
  _Bool _1;
  int _2;
  int _3;
  long long unsigned int _6;

  _1 = a_4(D) < b_5(D);
  _2 = (int) _1;
  _3 = -_2;
  _6 = (long long unsigned int) _3;
  return _6;
}

Then, it is expanded as a sign_extend:DI of a subreg:SI, and nowhere
does it see this isn't necessary (it isn't because that SI cannot be
negative).

The RTL code isn't optimised very well before combine, and that does

Trying 11 -> 12:
   11: {r128:SI=ca:SI-0x1;clobber ca:SI;}
      REG_UNUSED ca:SI
   12: r123:DI=sign_extend(r128:SI)
      REG_DEAD r128:SI
Failed to match this instruction:
(set (reg:DI 123)
    (sign_extend:DI (plus:SI (reg:SI 98 ca [+4 ])
            (const_int -1 [0xffffffffffffffff]))))

(note everything is made SImode in insn 11 before, it absorbed the
subreg).  Combine cannot keep track of known zero bits of hard regs
well, so it fails to see that XER[CA] is only ever 0 or 1 here (it
always is, but it doesn't know that either).

I'll try to add an extra pattern for this extend, that will do the
trick I think.