[Bug target/94735] MVE vector load/store pair getting removed with -O2.

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94735

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by SRINATH PARVATHANENI
<sripar01@gcc.gnu.org>:

https://gcc.gnu.org/g:aac5ae144363dbd857654511fbf335e53c8f7cf5

commit r10-8312-gaac5ae144363dbd857654511fbf335e53c8f7cf5
Author: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Date:   Tue Jun 16 12:53:23 2020 +0100

    arm: Correct the grouping of operands in MVE vector scatter store
intrinsics (PR94735).

    The operands in RTL patterns of MVE vector scatter store intrinsics are
    wrongly grouped, because of which few vector loads and stores instructions
    are wrongly getting optimized out with -O2.

    A new predicate "mve_scatter_memory" is defined in this patch, this
predicate
    returns TRUE on matching: (mem(reg)) for MVE scatter store intrinsics.
    This patch fixes the issue by adding define_expand pattern with
    "mve_scatter_memory" predicate and calls the corresponding define_insn by
    passing register_operand as first argument. This register_operand is
extracted
    from the operand with "mve_scatter_memory" predicate in define_expand
pattern.

            Backported from mainline
            2020-06-04  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

    gcc/
            PR target/94735
            * config/arm/predicates.md (mve_scatter_memory): Define to
            match (mem (reg)) for scatter store memory.
            * config/arm/mve.md (mve_vstrbq_scatter_offset_<supf><mode>):
Modify
            define_insn to define_expand.
            (mve_vstrbq_scatter_offset_p_<supf><mode>): Likewise.
            (mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
            (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
            (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
            (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
            (mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
            (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
            (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
            (mve_vstrhq_scatter_offset_fv8hf): Likewise.
            (mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
            (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
            (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
            (mve_vstrwq_scatter_offset_fv4sf): Likewise.
            (mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
            (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
            (mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
            (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
            (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
            (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
            (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
            (mve_vstrbq_scatter_offset_<supf><mode>_insn): Define insn for
scatter
            stores.
            (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
            (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
            (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
            (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
            (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
            (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
            (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
            (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
            (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
            (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
            (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
            (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
            (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
            (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
            (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
            (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
            (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
            (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
            (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
            (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.

    gcc/testsuite/
            PR target/94735
            * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_base.c: New
test.
            * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_base_p.c:
Likewise.
            * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_offset.c:
Likewise.
            * gcc.target/arm/mve/intrinsics/mve_vstore_scatter_offset_p.c:
Likewise.
            *
gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c:
            Likewise.
            *
gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c:
            Likewise.