[Bug target/93304] New: RISC-V: Function with interrupt attribute use register without save/restore at prologue/epilogue

[kito at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93304

            Bug ID: 93304
           Summary: RISC-V: Function with interrupt attribute use register
                    without save/restore at prologue/epilogue
           Product: gcc
           Version: 9.2.1
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: kito at gcc dot gnu.org
  Target Milestone: ---
            Target: riscv64-unknown-elf

Function with interrupt attribute use register without save/restore at
prologue/epilogue.

The problem is come from register rename pass, it use register not handled at
prologue/epilogue, but it's because RISC-V didn't implement
HARD_REGNO_RENAME_OK.

Version: GCC 8, 9, trunk

Option: -O -frename-registers -march=rv64i -mabi=lp64

Testcase:

static unsigned _timer_ticks = 0;

void m_timer_interrupt(void) __attribute__((interrupt));
void m_timer_interrupt(void)
{
  _timer_ticks ++;
}

Code gen (by e4a5f73449d7352ba8128fecbc9a9570d746abdb):
m_timer_interrupt:
        addi    sp,sp,-16
        sw      a4,12(sp)
        sw      a5,8(sp)
        lui     a4,%hi(_timer_ticks)
        lw      a5,%lo(_timer_ticks)(a4)
        addi    t0,a5,1                   #
        sw      t0,%lo(_timer_ticks)(a4)  # t0 are used but it not save/restore
at prologue/epilogue
        lw      a4,12(sp)
        lw      a5,8(sp)
        addi    sp,sp,16
        mret



Reported by goxinxog@gmail.com at RISC-V SW Dev 
 list
(https://groups.google.com/a/groups.riscv.org/d/msg/sw-dev/w8CCfQwk5DA/ZC0izJvBCAAJ)