[Bug rtl-optimization/93565] [9/10 regression] Combine duplicates instructions
segher at gcc dot gnu.org
gcc-bugzilla@gcc.gnu.org
Sat Feb 15 00:46:00 GMT 2020
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93565
--- Comment #22 from Segher Boessenkool <segher at gcc dot gnu.org> ---
T0 T2 T3 T4
alpha 6049096 100.020% 100.018% 100.001%
arc 4019384 100.000% 99.989% 99.989%
arm 14177962 99.999% 99.999% 100.000%
arm64 12968466 99.938% 99.888% 100.000%
c6x 2346077 100.000% 100.001% 100.001%
csky 3332454 100.000% 100.000% 100.000%
h8300 1165256 99.999% 99.999% 100.000%
i386 11227764 100.001% 100.001% 100.000%
ia64 18088488 100.003% 100.007% 100.003%
m68k 3716871 100.000% 100.000% 100.000%
microblaze 4935181 100.000% 99.995% 99.995%
mips 8407681 100.000% 100.000% 100.000%
mips64 6979344 99.987% 99.981% 99.981%
nds32 4471023 100.000% 99.994% 99.994%
nios2 3643253 100.000% 99.999% 99.999%
openrisc 4182200 100.000% 99.995% 99.995%
parisc 7710095 100.001% 100.001% 100.000%
parisc64 8676725 100.003% 100.002% 99.999%
powerpc 10603859 100.000% 100.000% 100.001%
powerpc64 17552718 100.007% 100.005% 99.999%
powerpc64le 17552718 100.007% 100.005% 99.999%
riscv32 1546172 100.000% 99.999% 99.999%
riscv64 6623170 100.010% 100.005% 100.001%
s390 13103095 99.995% 99.993% 99.999%
sh 3216555 99.999% 99.992% 99.993%
shnommu 1611176 99.999% 99.999% 100.000%
sparc 4363333 100.000% 99.997% 99.997%
sparc64 6751939 100.000% 99.997% 99.997%
x86_64 19681173 100.000% 100.000% 100.000%
xtensa 0 0 0 0
T0 is orig, T2 is only sign_extend, T3 is sign_extend and no same sources,
T4 is only no same source (SET_SRC).
The diffs look less than they are, this is just size, and with 2-2 combines
size does not change (on many targets). For powerpc, *all* the changes
these patches make hurt code quality (they change two parallel insns to
two sequential ones).
I think combine should just do what it already does, and you should add
some peepholes, or maybe some new pass?
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