[Bug rtl-optimization/93264] [10 Regression] ICE in cfg_layout_redirect_edge_and_branch_force, at cfgrtl.c:4522

[zhroma at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93264

--- Comment #5 from Roman Zhuykov <zhroma at gcc dot gnu.org> ---
Created attachment 47820
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=47820&action=edit
Considered "moving sms earlier" patch

I haven't tested "moving sms earlier" patch since 2011.  But I remember there
were some testsuite items where it makes difference, not sure whether it was
arm or ia64 platform.  I decided those passes between substantially change the
loop code and DDG.

I'll run some cross-testing to check how it works for now.

> In general it's a bad idea to try go "back" to CFG layout mode and the fix is
> to not do that.
Also qouting https://gcc.gnu.org/ml/gcc-patches/2020-02/msg00714.html:

> I think the expectation that you can go back to CFG layout mode
> and then work with CFG layout tools after we've lowered to CFG RTL
> is simply bogus.  Yeah, you can probably do analysis things but
> I wouldn't be surprised if a CFG RTL -> CFG layout -> CFG RTL cycle 
> can wreck things.  Undoubtedly doing CFG manipulations is not going
> to work since CFG layout does not respect CFG RTL restrictions.
> Partitioning simply uncovered latent bugs, there's nothing wrong
> with it IMHO.
There are two more passes re-entering cfg layout: pass_reorder_blocks and
pass_machine_reorg.