[Bug target/92190] [10 Regression] ICE in sp_valid_at, at config/i386/i386.c:6162 since r276648

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92190

--- Comment #17 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:b7b3378f91c0641f2ef4d88db22af62a571c9359

commit r10-6451-gb7b3378f91c0641f2ef4d88db22af62a571c9359
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Feb 5 15:38:49 2020 +0100

    i386: Omit clobbers from vzeroupper until final [PR92190]

    As mentioned in the PR, the CLOBBERs in vzeroupper are added there even for
    registers that aren't ever live in the function before and break the
    prologue/epilogue expansion with ms ABI (normal ABIs are fine, as they
    consider all [xyz]mm registers call clobbered, but the ms ABI considers
    xmm0-15 call used but the bits above low 128 ones call clobbered).
    The following patch fixes it by not adding the clobbers during vzeroupper
    pass (before pro_and_epilogue), but adding them for -fipa-ra purposes only
    during the final output.  Perhaps we could add some CLOBBERs early (say for
    df_regs_ever_live_p regs that aren't live in the live_regs bitmap, or
    depending on the ABI either add all of them immediately, or for ms ABI add
    CLOBBERs for xmm0-xmm5 if they don't have a SET) and add the rest later.
    And the addition could be perhaps done at other spots, e.g. in an
    epilogue_completed guarded splitter.

    2020-02-05  Jakub Jelinek  <jakub@redhat.com>

        PR target/92190
        * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Only
        include sets and not clobbers in the vzeroupper pattern.
        * config/i386/sse.md (*avx_vzeroupper): Require in insn condition that
        the parallel has 17 (64-bit) or 9 (32-bit) elts.
        (*avx_vzeroupper_1): New define_insn_and_split.

        * gcc.target/i386/pr92190.c: New test.