[Bug target/97417] RISC-V Unnecessary andi instruction when loading volatile bool

[jiawei at iscas dot ac.cn]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417

--- Comment #59 from jiawei <jiawei at iscas dot ac.cn> ---
   Hi Kito,

   Okay, I will retest the benchmark on gem5.



   发自我的小米手机在 "kito at gcc dot gnu.org"
   <gcc-bugzilla@gcc.gnu.org>，2020年12月25日 上午11:31写道：

     https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417

     --- Comment #58 from Kito Cheng <kito at gcc dot gnu.org[1]> ---
     Hi jiawei:

     I would suggest you just using inst count rather than cycle or
     time for
     measuring benchmark if you using qemu, since qemu is functional
     simulator not
     cycle accurate neither nearly-cycle accurate simulator, so the
     performance
     number is coming from your native host (x86_64) cpu, and it also
     might
     sensitive on your host loading. or maybe you could try gem5 for
     that?

     Thanks your helping benchmark that :)

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