[Bug target/98161] [11 Regression] Incorrect stack realignment on __force_align_arg_pointer__ with -msse4 by r11-446

cvs-commit at gcc dot gnu.org gcc-bugzilla@gcc.gnu.org
Sun Dec 6 20:57:30 GMT 2020


https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98161

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by H.J. Lu <hjl@gcc.gnu.org>:

https://gcc.gnu.org/g:6643ca0be6f34786b686415e457de96d0d9fbd2d

commit r11-5806-g6643ca0be6f34786b686415e457de96d0d9fbd2d
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Sun Dec 6 10:43:16 2020 -0800

    x86: Check mode of pseudo register push

    commit 266f44a91c0c9705d3d18e82d7c5bab32927a18f
    Author: H.J. Lu <hjl.tools@gmail.com>
    Date:   Sun May 17 10:10:34 2020 -0700

        x86: Allow V1TI vector register pushes

        Add V1TI vector register push and split it after reload to a sequence
        of:

        (set (reg:P SP_REG) (plus:P SP_REG) (const_int -8)))
        (set (match_dup 0) (match_dup 1))

    added a pseudo register push check.  But

    (insn 13 12 14 3 (set (mem:SI (pre_dec:SI (reg/f:SI 7 sp)) [0  S4 A32])
            (reg/v:SI 87 [ srclen ])) "x.c":37:16 54 {*pushsi2}
         (expr_list:REG_DEAD (reg/v:SI 87 [ srclen ])
            (expr_list:REG_ARGS_SIZE (const_int 4 [0x4])
                (nil))))

    is not a pseudo register push.  In 64-bit mode, mode of pseudo register
    push is TImode.  In 32-bit mode, it is DImode.  Add pseudo register push
    mode check to pseudo_reg_set.

    gcc/

            PR target/98161
            * config/i386/i386-features.c (pseudo_reg_set): Check mode of
            pseudo register push.

    gcc/testsuite/

            * gcc.target/i386/pr98161.c: New test.


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