[Bug target/94530] [9/10 Regression] ICE: SIGSEGV in rhs_regno (rtl.h:1924) with -Os -mcpu=falkor -mpc-relative-literal-loads -mcmodel=large

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94530

ktkachov at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2020-04-08
                 CC|                            |ktkachov at gcc dot gnu.org
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW

--- Comment #1 from ktkachov at gcc dot gnu.org ---
Confirmed.
In the code
538   if (!aarch64_classify_address (&addr, XEXP (x, 0), mode, true))
539     return false;
540
541   unsigned regno = REGNO (addr.base);
542   if (global_regs[regno] || fixed_regs[regno])
543     return false;

addr.base is not guaranteed to be a register. In this instance it's:
(mem/u/c:DI (symbol_ref/u:DI ("*.LC1") [flags 0x2]) [0  S8 A64])