[Bug target/91683] ICE: SIGSEGV at -O when compiling for riscv64

[rguenther at suse dot de]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91683

--- Comment #15 from rguenther at suse dot de <rguenther at suse dot de> ---
On September 10, 2019 3:50:46 AM GMT+02:00, "wilson at gcc dot gnu.org"
<gcc-bugzilla@gcc.gnu.org> wrote:
>https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91683
>
>--- Comment #14 from Jim Wilson <wilson at gcc dot gnu.org> ---
>> 3) Do we want to prohibit calling gen_reg_rtx during combine?  Why
>did
>> we want it, before?
>
>Prohibiting gen_reg_rtx calls here would have helped find the bugs I'm
>fixing
>now.  I've got a hack to do this to find the remaining bugs I need to
>fix.
>
>I don't know why anyone would want it before.  I'm not sure if this
>ever worked
>right.

I still don't understand. The rtx are not relocated. The only thing is the
address of the slot of the regno to rtx map.