[Bug target/89400] [7/8/9 Regression] ICE: output_operand: invalid %-code with -march=armv6kz -mthumb -munaligned-access

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89400

--- Comment #8 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Author: rearnsha
Date: Thu Oct 17 16:45:46 2019
New Revision: 277123

URL: https://gcc.gnu.org/viewcvs?rev=277123&root=gcc&view=rev
Log:
[arm]  PR target/89400 fix thumb1 unaligned access expansion

Armv6 has support for unaligned accesses to memory.  However, the
thumb1 code patterns were trying to use the 32-bit code constraints.
One failure mode from this was that the patterns are designed to be
compatible with conditional execution and this was then causing an
assert in the compiler.

The unaligned_loadhis pattern is only used for expanding extv, which
in turn is only enabled for systems supporting thumb2.  Given that
there is no simple expansion for a thumb1 sign-extending load (the
instruction has no immediate offset form and requires two registers in
the address) it seems simpler to just disable this for thumb1.

Fixed thusly:

        Backport from trunk:
        2019-05-03  Richard Earnshaw  <rearnsha@arm.com>

        PR target/89400
        * config/arm/arm.md (unaligned_loadsi): Add variant for thumb1.
        Restrict 'all' variant to 32-bit configurations.
        (unaligned_loadhiu): Likewise.
        (unaligned_storehi): Likewise.
        (unaligned_storesi): Likewise.
        (unaligned_loadhis): Disable when compiling for thumb1.

Modified:
    branches/gcc-9-branch/gcc/ChangeLog
    branches/gcc-9-branch/gcc/config/arm/arm.md