[Bug target/89835] New: The RISC-V target uses amoswap.w for relaxed stores
mikulas at artax dot karlin.mff.cuni.cz
gcc-bugzilla@gcc.gnu.org
Tue Mar 26 19:51:00 GMT 2019
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89835
Bug ID: 89835
Summary: The RISC-V target uses amoswap.w for relaxed stores
Product: gcc
Version: 8.3.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: mikulas at artax dot karlin.mff.cuni.cz
Target Milestone: ---
Stores with memory_order_relaxed can be implemented as simple store
instructions. For the RISC-V target, gcc generates less efficient atomic
instruction amoswap.w.
Try to compile with code with "riscv64-linux-gnu-gcc-8 -S -o - -O2 relaxed.c":
#include <stdatomic.h>
_Atomic int value;
int load(void)
{
return atomic_load_explicit(&value, memory_order_relaxed);
}
void store(int x)
{
atomic_store_explicit(&value, x, memory_order_relaxed);
}
Result:
.file "relaxed.c"
.option pic
.text
.align 1
.globl load
.type load, @function
load:
la a5,value
lw a0,0(a5)
sext.w a0,a0
ret
.size load, .-load
.align 1
.globl store
.type store, @function
store:
la a5,value
amoswap.w zero,a0,0(a5)
ret
.size store, .-store
.comm value,4,4
.ident "GCC: (Debian 8.3.0-2) 8.3.0"
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