[Bug target/89411] RISC-V backend will generate wrong instruction for longlong type like lw a3,-2048(a5)

[wilson at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89411

Jim Wilson <wilson at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED
           Assignee|unassigned at gcc dot gnu.org      |wilson at gcc dot gnu.org

--- Comment #6 from Jim Wilson <wilson at gcc dot gnu.org> ---
Fixed, with testcase added.