[Bug target/89607] Missing optimization for store of multiple registers on aarch64

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89607

--- Comment #7 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Yichao Yu from comment #6)
> > For aarch64, there was talk about adding stp for q registers.
> 
> What do you mean? I was initially unsure about it too but I assume it
> already exist since clang (and now GCC 9) emits it and the arm arch
> reference manual also mentions it without mentioning it only available in a
> later version.

I mean the support to emit stp for q registers.  I did not follow the disussion
close enough but from your mention, it was committed.
The problem with stp for q registers on some targets is that it is single issue
or it is split into two instructions anyways.