[Bug rtl-optimization/87763] [9 Regression] aarch64 target testcases fail after r265398

rearnsha at gcc dot gnu.org gcc-bugzilla@gcc.gnu.org
Wed Jan 23 14:40:00 GMT 2019


--- Comment #28 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Yes, it's always possible to write patterns for this, but as you point out, we
end up with many variants: insert in bottom (no left shift), insert in top
(left shift then doesn't need an additional AND mask because there are no top
bits to remove) and insert in middle.

The matching of all the immediate values to ensure that the insn makes sense is
not all that trivial - and you have to then convert those into the relevant bit
offsets during assembly output.

Finally, of course, we still have to deal with the fact that the compiler
might, somehow decide to canonicalize a pattern into the existing zero_extract
bit-field insert idiom, so we don't get to remove any insns.

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