[Bug target/88808] bitwise operators on AVX512 masks fail to use the new mask instructions

ubizjak at gmail dot com gcc-bugzilla@gcc.gnu.org
Sat Jan 12 11:01:00 GMT 2019


--- Comment #2 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Jakub Jelinek from comment #1)
> See PR88473 and PR88798.  I'd personally probably revert the changes to make
> the mask operations separate from GPR operations and just use special RTL
> patterns if GPR operation can't do it (e.g. andn when not BMI, or 64-bit
> logicals on 32-bit targets), but it is too late for that for GCC9.

I'm not against the revert, [1] describes the rationale for the current
approach from 2016. In the meantime, a couple of new constraint modifiers were
introduced to better guide register allocation choices, and I believe that with
appropriate RTX costs, it is possible to implement mask operations without

I certainly agree with Jakub to postpone new implementation to gcc-10. Without
approporate cost model, we risk that under register pressure, RA will allocate
mask registers for values, expected to live in general registers. At the time,
it was warned that moves between mask and integer registers are quite costly,
so we took the safe way and by introducin UNSPECs, avoided runtime regressions
when mask registers were present.

[1] https://gcc.gnu.org/ml/gcc-patches/2016-11/msg02612.html

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