[Bug c/89482] New: arm aarch32 inline assembly w constraints generate s registers instead of d

[ciro.santilli at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89482

            Bug ID: 89482
           Summary: arm aarch32 inline assembly w constraints generate s
                    registers instead of d
           Product: gcc
           Version: 8.2.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: ciro.santilli at gmail dot com
  Target Milestone: ---

The 8.2.0 documentation at
https://gcc.gnu.org/onlinedocs/gcc-8.2.0/gcc/Machine-Constraints.html#Machine-Constraints
says:

t
VFP floating-point registers s0-s31. Used for 32 bit values.

w
VFP floating-point registers d0-d31 and the appropriate subset d0-d15 based on
command line options. Used for 64 bit values only. Not valid for Thumb1.

However, when I try to compile the following:

main.c

````
#include <assert.h>

int main(void) {
    float my_float = 1.5;
    __asm__ (
        "vmov s0, 1.0;"
        "vadd.f32 %[my_float], %[my_float], s0;"
        : [my_float] "+t" (my_float)
        :
        : "s0"
    );
    assert(my_float == 2.5);

#if 1
    double my_double = 1.5;
    __asm__ (
        "vmov.f64 d0, 1.0;"
        "vadd.f64 %[my_double], %[my_double], d0;"
        : [my_double] "+w" (my_double)
        :
        : "d0"
    );
    assert(my_double == 2.5);
#endif
}
````

with:

    arm-linux-gnueabihf-gcc -std=c99 -ggdb3 -march=armv7-a -pedantic -Wall
-Wextra -o 'main' 'main.c'

the part in #if 1 would fail with:

    selected FPU does not support instruction -- `vadd.f64 s14,s14,d0'

so it appears that the "w" constraint is actually being converted to an s
register.

Tested in Ubuntu 18.10, packaged GCC 8.2.0, mentioned at:
https://stackoverflow.com/questions/53960240/armv8-floating-point-output-inline-assembly