[Bug target/89411] RISC-V backend will generate wrong instruction for longlong type like lw a3,-2048(a5)

[wilson at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89411

Jim Wilson <wilson at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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                 CC|                            |wilson at gcc dot gnu.org

--- Comment #1 from Jim Wilson <wilson at gcc dot gnu.org> ---
I think the problem is in riscv_valid_lo_sum_p where we do
  /* We may need to split multiword moves, so make sure that each word          
     can be accessed without inducing a carry.  */
  if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
      && (!TARGET_STRICT_ALIGN
          || GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode)))
    return false;

The problem is that this doesn't work for BLKmode, as GET_MODE_SIZE,
GET_MODE_BITSIZE, and GET_MODE_ALIGNMENT don't return usable values for
BLKmode.  We could perhaps just return false for mode == BLKmode here, but that
requires some testing to see what conditions BLKmode might appear here.  We
don't want to accidentally disable this optimization when it is useful and
safe.

Best case solution is probably to pass down a decl or a MEM, so we can get the
actual size and alignment from there.  That is a little bit more work, so I
only want to do that if necessary.